Semiconductor device

ABSTRACT

A semiconductor device having a plurality of cascaded IC&#39;s ( 14, 15, 16 ), wherein the matching impedance between a signal transmission path ( 12 ) connected to an external signal transmission path and an input-side or output-side IC ( 14, 16 ) is set at 50 ohms which is equal to the characteristics impedance of the external signal transmission path. The matching impedance between a internal signal transmission path ( 13 ) and an input-side or output-side IC or intermediate IC is set at 200 ohms which is higher than the 50 ohms. The semiconductor device reduces the current dissipation and can operate at a higher speed.

TECHNICAL FIELD

The present invention relates to a semiconductor device having aplurality of semiconductor integrated circuits (ICs) such as an MCM(Multi Chip Module), and more particularly, to a semiconductor devicehaving an input impedance matched to the impedance of an externalcircuit and capable of performing a high-speed operation.

BACKGROUND ART

Together with a recent tendency of higher degree of integration densityof semiconductor devices, there has been an increasing demand for ahigher-speed operation. In an optical communication system, for example,data transfer rate has been significantly increased and data transferrates of 2.4 Gbps and 10 Gbps have already been realized in practicaluse. In the future, the data transfer rate is expected to be increasedmore and more.

As the operational speed of the semiconductor device becomes higher, itis impossible to ignore the presence of a reflected signal generated ina transmission path that connects together interconnections within asemiconductor integrated circuit (IC) or connects the semiconductor ICwith another semiconductor IC. Therefore, a technique of impedancematching is used in a portion having a long interconnection or longtransmission path.

FIG. 9 shows the configuration of a module in a conventionalsemiconductor device. A semiconductor device 21 has input/outputconnectors 27 connected to an external circuit. Each terminal of theconnector 27 is connected to a corresponding input/output transmissionpath 22. Disposed on a mounting substrate/board 28 are a plurality ofcascaded IC chips. More specifically, an input-side IC chip 24 and anoutput-side IC chip 26, which are connected to the input/outputtransmission paths 22, and the intermediate IC chips 25 are disposed onthe mounting substrate/board 28. Each adjacent two of the IC chipsdisposed are connected together by one or more internal transmissionpaths 23 formed on the mounting substrate/board 28. Each of theconnectors 27 is connected to a coaxial cable (not shown), through whicha signal is exchanged between the semiconductor device 21 and theexternal circuit. Here, a propagation in the coaxial transmission pathwill be described. Attenuation constant α is represented by thefollowing equation: $\begin{matrix}{\alpha = {{\frac{1}{4\quad\pi}\frac{Rs}{\sqrt{\frac{\mu_{0}}{ɛ}\ln\frac{D}{d}}}} = \left( {\frac{1}{d} + \frac{1}{D}} \right)}} & (1)\end{matrix}$where d is the outer diameter of a central conductor, D is the innerdiameter of an outside conductor, ε is the dielectric constant ofinsulator, Rs is the surface resistance, and μ₀ is the magneticpermeability of vacuum.

A smaller value of the α reduces the attenuation in the coaxialtransmission path. In the above equation (1), from the view point of therelation between the ratio of D to d and α, if D/d=3.59, then α assumesa minimum value. The characteristic impedance of the coaxial cable isrepresented by the following equation: $\begin{matrix}{Z_{0} = {\frac{60}{\sqrt{ɛ_{r}}}\ln\frac{D}{d}}} & (2)\end{matrix}$where ε_(r) is the relative dielectric constant of insulator.

The coaxial cable uses polyethylene resin (ε_(r)=2.3) as an insulator tosupport the central conductor. When this relative dielectric constant isassigned to the coaxial cable using the support for the centralconductor, the characteristic impedance is about 50 Ω (ohms) at thepoint of D/d=3.59, where the attenuation constant assumes the minimumvalue. Therefore, the external impedance is generally set at 50 ohms.The characteristic impedance of the input/output transmission path 22 isaccordingly set at 50 ohms in order to achieve the impedance matching tothe external impedance. At the same time, the characteristic impedanceof the internal transmission path 23 is also set at 50 ohms. Theinput/output impedance of the ICs (24 to 26) that perform a high-speedoperation is also set at 50 ohms.

In the conventional technique, in order to set the input/outputimpedance of IC at 50 ohms, the input circuit of the IC is connected toa matching resistor of 50 ohms and, at the same time, the output circuitof the IC is also connected to another matching resistor of 50 ohms.Therefore, the output transistor of the IC is driven by a low loadresistance. In the IC to which an output signal from the outputtransistor is input, the amplitude of the input signal is defined inorder to guarantee a normal operation of the IC on the signal inputside. The output transistor on the preceding-stage IC operates to meetthe defined amplitude. However, being connected to a low load resistanceas described above, the output transistor needs to be driven with alarge current in order to meet the requirement. As a result, thefollowing problems have arisen:

(1) The current dissipation of the ICs (24 to 26) and semiconductordevice (21) is increased because the output transistor is driven with alarge current.

(2) The size of the IC should be increased because the size of theoutput transistor needs to be increased.

(3) The current dissipation and the area of the IC are increased moreand more because the number of stages or the size of the buffer circuitfor driving the output transistor is increased.

DISCLOSURE OF THE INVENTION

In order to solve the problems in the conventional technique asdescribed above, it is an object of the present invention to provide ahigher-speed and lower-power-dissipation semiconductor device in whichthe impedance matching between the input/output of the IC chip and thetransmission path on the mounting substrate/board is achieved so as notto generate a signal reflection or signal loss even in a higher-speedoperation, to thereby reduce the output drive current of the IC chip.

The present invention provides, in a first aspect thereof, asemiconductor device including a plurality of ICs including at least aninput-stage IC and an output-stage IC, and signal transmission pathsthat connect each two of the plurality of ICs to achieve impedancematching therebetween, characterized in that: an input impedance of theinput-stage IC and an output impedance of the output-stage IC are equalto a first impedance; and each of at least two of the plurality of ICsis impedance-matched to a corresponding one of signal transmission pathsat a matching impedance which is higher than the first impedance.

The present invention also provides, in a second aspect thereof asemiconductor device including a plurality of ICs including at least aninput-stage IC and an output-stage IC, and signal transmission pathsthat connect each adjacent two of the plurality of ICs to achieveimpedance matching therebetween, characterized in that: an inputimpedance of the input-stage IC and an output impedance of theoutput-stage IC are first impedance and second impedance, respectively;each of at least two of the plurality of ICs is impedance matched to acorresponding one of the signal transmission paths at a matchingimpedance higher than a lower one of the first and second impedances.

In accordance with the above configuration, the present inventionprovides the following advantages:

(1) Since the load impedance of the output circuit of the IC within thesemiconductor device is increased, the output current needed to obtainthe same output voltage can be reduced. Further, the number of stages ofthe buffers needed for the output circuit can be reduced to therebyreduce the current dissipation of the IC and the entire semiconductordevice.

(2) Since the operating current of the output transistor in the outputcircuit within the semiconductor device can be reduced, the size of theoutput transistor can be reduced and therefore the chip size of the ICchip can be reduced.

(3) Since the number of stages of the buffers in the output circuit ofthe IC within the semiconductor device can be reduced, operational speedof the IC and semiconductor device incorporating the same can beincreased.

The reason why the above advantages can be obtained will be describedbelow with reference to FIG. 10 showing a concrete example of aconventional IC that uses a bipolar transistor. Note that, in FIG. 10,the line A-A of the upper part should be coupled to the line A-A of thelower part. Here, Q6, Q7, Q11 to Q19, Q21 to Q27, Q31, Q32, and Q41 toQ43 are bipolar transistors, R7, R8, R11 to R14, R21 to R28, and R31 toR34 are resistors, GND is a ground line, and VEE is a power source line.

FIG. 10 shows the configuration of the connections between the outputcircuit 24 b of the input-side IC chip 24 and the input circuit 25 a ofthe intermediate IC chip 25. The input-side IC chip 24 on the precedingstage has thereon a flip-flop circuit 20 using an ECL (Emitter CoupledLogic) circuit. The output circuit 24 b of the input-side IC chip 24 isconnected through an internal transmission path 23 formed on a mountingsubstrate/board 28 to the input circuit 25 a of the intermediate IC chip25, which is connected to the IC chip on the succeeding stage. Theflip-flop circuit 20 is comprised of a core section (only a slavecircuit is shown in FIG. 10) of the flip-flop circuit and a two-stagebuffer circuit including a differential circuit and an emitter-followercircuit configuring the output circuit 24 b. The input circuit 25 a ofthe IC chip connected to the succeeding stage is configured by anemitter-follower circuit. The characteristic impedance of the internaltransmission path 23 on the mounting substrate/board 28 is 50 ohms,which is the same value of 50 ohms as the external impedance asdescribed above. Further, the impedances of load resistors R31 and R32on the last stage of the output circuit 24 b are set at 50 ohms so as toachieve the impedance matching to the internal transmission paths 23 onthe mounting substrate/board 28. Further, resistors R33 and R34 of 50ohms are connected to the input circuit 25 a on the succeeding stage soas to achieve the impedance matching to the internal transmission paths23 on the mounting substrate/board 28.

As described above, in the conventional semiconductor device, theimpedance matching between the input/output circuits of the IC chip andthe transmission path on the mounting substrate/board is achieved at 50ohms which is similar to the external impedance. Therefore, a signalreflection or signal loss does not occur in the design of theconventional semiconductor device even if a higher operational speed isemployed. In FIG. 10, the last-stage load resistor R31 (R32), which is50 ohms, and the matching resistor R33 (R34) of the input circuit 25 aon the succeeding stage, which is 50 ohms, are connected in parallel tothe transistor Q41 (Q42), whereby the output load of the flip-flopcircuit 20 on the preceding stage is 25 ohms. Assuming that the requiredoutput amplitude is 05 Vp-p, a current of 20 mA is needed for the outputdrive current of the flip-flop circuit 20 on the preceding stage.Therefore, the size of each of the last stage transistors Q41 to Q43 ofthe output circuit 24 b on the preceding stage needs to be large enoughto drive a 20 mA current. Further, the two-stage buffer circuit isnecessary in order to operate the large-sized transistor at a highspeed. Moreover, the size of each of the transistor Q31 and Q32 thatdrive the output transistors (Q41, Q42) must be increased. In theflip-flop circuit 20 on the preceding stage shown in FIG. 10, the coresection uses 2 μm×5 μm emitter size transistors and operates with adrive current of a 5 mA or less. In the output section, on the otherhand, 20 mA is required and therefore 2 μm×20 μm emitter sizetransistors (Q41 to Q43) are required for the last stage of the outputcircuit. Further, in order to drive the 2 μm×20 μm emitter sizetransistors on the last stage of the output circuit, the two-stagebuffer circuit configured by the differential circuit andemitter-follower circuit is required as a buffer circuit. Further, theemitter size of each of the transistors (Q31, Q32) that drive the largeemitter size transistors (Q41, Q42) needs to be increased up to 2 μm×10μm. Thus, there occurs that the current dissipation is increased, andthat the operational speed is lowered in some cases. Further, in thecase where a semiconductor device or MCM including a plurality of ICchips is formed on a mounting substrate/board, each IC output circuitneeds a current dissipation of 20 mA or more, resulting in a largecurrent dissipation in terms of the entire device.

In the semiconductor device shown in FIG. 9, the characteristicimpedance of the input/output transmission path 22 needs to be set at 50ohms and therefore the matching resistances of the input circuit of theinput-side IC chip 24 and the output circuit of the output-side IC chip26 are set at 50 ohms; however, the characteristic impedance of theinternal transmission path 23 that is not connected to the coaxial cableneed not be set at 50 ohms. The reason is as follows. Since the coaxialcable is generally used as a long transmission path, the characteristicimpedance thereof is set at 50 ohms in order to reduce the attenuation.In the case of the internal transmission path 23 having a small length,the importance need to be attached to the attenuation constant. Assumingthat the characteristic impedances of the input/output transmission path22 and the internal transmission path are Zex and Zint respectively, andthat the characteristic impedance of the internal transmission path 23is set so that Zint=αZex(α>1), each of the matching impedances of theoutput circuit of the input-side IC chip 24 and the input circuit of theintermediate IC chip 25 is a Zex, with the result that the loadimpedance of the output transistor of the input-side IC chip 24 isαZex/2. Assuming that the input signal amplitude needed to drive theintermediate IC chip 25 on the next stage is Vin, current I needed inthe case of the conventional circuit is represented by the followingequation:I=Vin/2αZexwhereas, in the case of the semiconductor device according to thepresent invention, the required current I is represented by thefollowing equation:I−Vin/2Zint=Vin/2αZex

In this case, 1/α is enough to drive the intermediate IC chip 25.Therefore, it is possible to reduce the size of the output transistorand thereby to reduce the number of stages and the size of the buffercircuit that drives the output transistor. Although the above advantagesof the present invention can be obtained so long as α>1, it ispreferable that 2<α<10 be satisfied. The reason is that the advantageobtained by the present invention is relatively limited if α is not morethan 2 and it may be impossible to ignore other adverse effects such asan increase in signal loss or signal delay if α is not less than 10.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram exemplifying a semiconductor device,according to the present invention, and FIG. 1B is a block diagramexemplifying a conventional semiconductor device;

FIG. 2 is a block diagram schematically exemplifying the configurationof the semiconductor device according to the present invention whichinclude interconnections other than transmission paths;

FIG. 3 is a perspective view of a semiconductor device according to afirst embodiment of the present invention;

FIG. 4 is a circuit diagram of the semiconductor device according to thefirst embodiment of the present invention;

FIG. 5 is a circuit diagram of a semiconductor device according to asecond embodiment of the present invention;

FIG. 6 is a circuit diagram of a semiconductor device according to athird embodiment of the present invention;

FIG. 7 is a block diagram of a semiconductor device according to afourth embodiment of the present invention;

FIG. 8 is a block diagram of a semiconductor device according to a fifthembodiment of the present invention;

FIG. 9 is a perspective view of a conventional semiconductor device; and

FIG. 10 is a circuit diagram of the conventional semiconductor device.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1A is a block diagram schematically exemplifying the configurationof the semiconductor device according to the present invention. As shownin the same drawing, a semiconductor device 100 includes a plurality ofICs disposed therein, including an input-stage IC 104, an output-stageIC 106, and one or more intermediate-stage IC 105, which are cascaded bysignal transmission paths. The signal transmission paths includeinput/output transmission paths 102 connected to external transmissionpaths 101 and one or more internal transmission paths 103 eachconnecting adjacent two of the ICs. Although the characteristicimpedance Z of the input/output transmission path 102 is set at 50 ohmsin order to achieve the impedance matching to the characteristicimpedance Z (Z=50 ohms) of the external transmission path 103, thecharacteristic impedance Z of the internal transmission path 103 is setat more than 50 ohms (e.g., Z=200 ohms). The input-side IC 104 oroutput-side IC 106 is disposed between the external transmission path101 and the internal transmission path 103, and the intermediate IC 105is disposed between two of the internal transmission paths 103. Theimpedances of the input/output circuits of each of the semiconductor ICsare set to match the characteristic impedances of the transmission pathsconnected to the respective input/output circuits. More specifically,the input impedance of an input circuit 104 a of the input-side IC 104is set at 50 ohms, the output impedance of an output circuit 104 b ofthe input-side IC 104 is set at more than 50 ohms, the input impedanceof an input circuit 105 a and the output impedance of an output circuit105 b of the intermediate IC 105 are set at more ta 50 ohms, the inputimpedance of an input circuit 106 a of the output-side IC 106 is set atmore than 50 ohms, and the output impedance of an output circuit 106 bof the output-side IC 106 is set at 50 ohms.

The semiconductor device 100 may have a modular configuration such as anMCM. The mounting substrate/board, on which the transmission paths areformed and the semiconductor ICs are mounted, may be a semiconductorsubstrate, an inorganic board made of ceramic, or a resin board made ofglass epoxy. Further, the mounting substrate/board may be aninsulator-coated metal board. In the case where the mountingsubstrate/board is a semiconductor substrate, devices such astransistors may be formed within the substrate. The transmission pathsmay be formed directly on a package, and the semiconductor integratedcircuits may be mounted directly on the package (mountingsubstrate/board may serve also as a package).

Although not shown in the semiconductor device of FIG. 1,interconnections other than the transmission path, such as a powersource line, are actually formed on the mounting substrate/board. Morespecifically, as shown in FIG. 2, interconnections 107 other thantransmission paths, such as a power source line, a ground line, and acontrol line are formed, if needed in addition to the input/outputtransmission paths 102 and internal transmission paths 103, on amounting substrate/board 100 a having thereon the ICs 104 to 106.However, the present invention is not focused on the interconnectionsother than the transmission paths, and is entirely focused on thetransmission paths.

The output signals of the input-side IC 104 and intermediate IC 105 maybe input to a plurality of ICs via transmission paths having branches.Further, passive components such as a capacitor or an inductor, or athin-film active component may be formed on the mountingsubstrate/board. Further, an active component or passive component otherthan a semiconductor integrated circuit may be separately mounted on themounting substrate/board. Each of the ICs 104 to 106 may be a bare chipIC or a packaged IC. Further, an MCM structure in which a plurality ofIC chips are mounted may be adopted.

The characteristic impedances of all the internal transmission paths 103need not be set at a fixed value. For example, the characteristicimpedances of some of internal transmission paths 103 may be 100 ohms,and the characteristic impedances of the other internal transmissionpaths 103 may be 200 ohms. Further, the characteristic impedances of allthe internal transmission paths 103 need not be more than thecharacteristic impedances of the input/output transmission paths. Onlythe characteristic impedances of some of the internal transmission paths103 may be set at not less than 50 ohms. The advantages of the presentinvention may be obtained when at least the characteristic impedances ofsome of the internal transmission paths 103 are set at more than thecharacteristic impedance of the input/output transmission paths.However, the maximum advantage will be obtained when the characteristicimpedances of all the internal transmission paths 103 are larger thanthe characteristic impedance of the input/output transmission paths. Interms of design man-hours or easiness of manufacturing, it is mostdesirable to set the characteristic impedances of all the internaltransmission paths 103 at a fixed value.

It is most preferable to use a coaxial cable as the externaltransmission path 101, in terms of signal transmission quality, easinessof connection, and reduction in design man-hours.

Although the transmission rate or frequency of the signal used in thesemiconductor device according to the present invention is notparticularly limited, the present invention is effectively applied tothe case where the signal transmission rate is higher than 1 Gbps orsignal frequency is higher than 800 MHz, in which the problem ofimpedance matching is of significant importance in view of reduction ofthe signal reflection. In particular, when a signal transfer rateexceeds 2.4 Gbps or a signal frequency exceeds 1 GHz, the problem ofimpedance matching becomes more serious, with the result that theadvantages of the present invention become more significant.

For comparison with the semiconductor device 100, a conventionalsemiconductor device is shown in FIG. 1B. In FIG. 1B, reference numeralsfor the components include least significant two digits which are commonto the least significant two digits of the reference numerals used forthe corresponding components in the semiconductor device of FIG. 1A, andduplicated description of these components will be omitted herein. Inthe conventional technique, the characteristic impedances of all thetransmission paths are set at the same value of 50 ohms as thecharacteristic impedance of the external transmission path, andinput/output impedances of all the input/output circuits of respectiveICs are set at 50 ohms.

FIRST EMBODIMENT

FIG. 3 is a perspective view showing the configuration of asemiconductor device according a first embodiment of the presentinvention. In FIG. 3, reference numerals for the components include theleast significant digit which is common to the least significant digitof the reference numerals for the corresponding components in theconventional semiconductor device of FIG. 9, and duplicated descriptionof these components will be omitted herein. In the present embodiment,the characteristic impedances of the input/output transmission paths 12that are connected to respective external circuits through theconnectors 17 are set at the same value of 50 ohms as the externalimpedance; whereas the characteristic impedances of the internaltransmission paths 13 that connect together a plurality of IC chips areset at 200 ohms, which is higher than the external impedance. The inputimpedance of the input circuit of the input-side IC chip 14 and theoutput impedance of the output circuit of the output-side IC chip 16 areset at 50 ohms so as to match the characteristic impedances of theinput/output transmission paths 12; whereas the output impedance of theinput-side IC chip 14, the input impedance of the output-side IC chip16, and the input/output impedances of the intermediate IC chip 15 areset at 200 ohms, which is higher than the external impedance. That is,the input impedance of the input-side IC chip 14 that incorporatestherein the input circuits of the entire semiconductor device 11 is setat 50 ohms and the output impedance thereof is set at 200 ohms. On theother hand, the input impedance of the output-side IC chip 16 thatincorporates therein the output circuits of the entire semiconductordevice is set at 200 ohms and the output impedance thereof is set at 50ohms.

With reference to FIG. 4, the configuration of the connections betweenthe IC chips within the semiconductor device will now be described.Here, connections between an output circuit 14 b of the input-side ICchip 14 and an input circuit 15 a of the intermediate IC chip 15 isshown as an example, wherein the input-side and intermediate IC chipsinclude therein bipolar transistors. In FIG. 4, Q1 to Q7 are bipolartransistors, R1 to R8 are resistors, GND is a ground line, and VEE is apower source line. The output circuit 14 b of the input-side IC chip 14is configured by an emitter-follower circuit and a differential circuit.The load resistors R3 and R4 of the last stage are set at 200 ohms. Theinput circuit 15 a of the intermediate IC chip 15, which is connected tothe input-side IC chip 14 as the IC chip of the succeeding stage, isconfigured by an emitter-follower circuit. The matching resistors R5 andR6 of 200 ohms are set in the input section of the intermediate IC chip15. The output circuit 14 b of the input-side IC chip 14 on thepreceding stage and the input circuit 15 a of the intermediate IC chip15 on the succeeding stage are connected to each other through theinternal transmission paths 13 each formed on a mounting substrate/board18 and having a characteristic impedance of 200 ohms. Thus, impedancematching is achieved. The load resistors R3 and R4 of the precedingstage, which are 200 ohms, and the matching resistors R5 and R6 of thesucceeding-stage input circuit 15 a, which are 200 ohms, allow theoutput load of the output circuit 14 b on the preceding stage to assume100 ohms. Assuming that the output amplitude is 0.5 Vp-p, the outputdrive current needed for the output circuit 14 b on the preceding stageis 5 mA, thereby reducing the current dissipation.

Further, in the case where a semiconductor device or MCM having aplurality of IC chips is formed on the mounting substrate/board, thecurrent dissipation of 20 mA, which has been required for respective ICoutput circuits in the prior art, may be reduced to ⅕ in the presentembodiment. Thus, the current dissipation of the entire semiconductordevice is significantly reduced.

Although the input matching resistors R5 and R6 are connected betweenthe base of the transistor Q6 and ground and between the base of thetransistor Q7 and ground, respectively, in the present embodiment, theinput matching resistor may be connected between the base and the powersource line depending on the circuit scheme.

SECOND EMBODIMENT

FIG. 5 shows a part of the circuit configuration of a semiconductordevice according to a second embodiment of the present invention. Theentire configuration of the semiconductor device according to the secondembodiment is similar to that of the second embodiment shown in FIG. 3.More specifically, FIG. 5 shows the configuration of connections betweenthe input-side IC chip 14 and the intermediate IC chip 15. In FIG. 5, Q1to Q7 and Q11 to Q19 are bipolar transistors, R1 to R8 and R11 to R14are resistors, GND is a ground line, and VEE is a power source line. Aflip-flop circuit 10 using an ECL basic circuit is mounted on theinput-side IC chip 14 on the preceding stage. The output circuit 14 b ofthe input-side IC chip 14 and input circuit 15 a of the intermediate ICchip 15 on the succeeding stage are connected to each other through theinternal transmission paths 13 formed on a mounting substrate/board 18.The flip-flop circuit 10 is configured by a core section (only a slavecircuit is shown in FIG. 5) of the flip-flop circuit and a one-stagebuffer circuit including an emitter-follower circuit and a differentialcircuit. The load resistors R3 and R4 on the last stage are set at 200ohms, respectively. The input circuit 15 a of the intermediate IC chip15, which is connected to the output circuit 14 b of the input-side ICchip 14 as the IC chip on the succeeding stage, is configured by anemitter-follower circuit. The matching resistors R5 and R6 of 200 ohmsare set in the input section. The output circuit 14 b of the flip-flopcircuit 10 on the preceding stage and the input circuit 15 a of theintermediate IC chip 15 on the succeeding stage are connected to eachother through the internal transmission paths 13 each formed on themounting substrate/board 18 and having a characteristic impedance of 200ohms. Thus, impedance matching is achieved. The load resistors R3 and R4on the last stage, which are 200 ohms, and the matching resistors R5 andR6 of the succeeding-stage input circuit 15 a, which are 200 ohms, allowthe output load of the flip-flop circuit 10 on the preceding stage toassume 100 ohms. Assuming that the output amplitude is 0.5 Vp-p, theoutput drive current needed for the output circuit of the flip-flopcircuit 10 on the preceding stage is 5 mA, thereby reducing the currentdissipation. In the conventional case, an output drive current of 20 mAhas been required and therefore the last stage of the output circuit hasbeen configured by transistors each having a large emitter size of 2μm×20 μm. On the other hand, in the present invention, the requiredoutput drive current is reduced to 5 mA, whereby the last stage of theoutput circuit may be configured by transistors each having the sameemitter size of 2 μm×5 μm as the emitter size of transistor to be usedin the core section of the flip-flop circuit. For the configuration ofICs, there was a need to drive large-sized transistors on the laststage, which requires a two-stage buffer circuit including adifferential circuit or emitter-follower circuit; whereas, in thepresent invention, the sizes of the transistors on the last stage arereduced, whereby a one-stage buffer circuit is enough for the driving.Thus, it is possible to operate the IC at a higher speed by reducing thecurrent dissipation of the entire IC and the number of buffer circuits.

THIRD EMBODIMENT

FIG. 6 shows a part of the circuit configuration of a semiconductordevice according to a third embodiment of the present invention. Theentire configuration of the semiconductor device according to the thirdembodiment is similar to that of the second embodiment shown in FIG. 3.More specifically, FIG. 6 shows the configuration of connections betweenthe input-side IC chip 14 and the intermediate IC chip 15. In FIG. 6, T1to T7 are field-effect transistors, R1 to R8 are resistors, VCC is apower source line, and GND is a ground line. The output circuit 14 b ofthe input-side IC chip 14 is configured by a source-follower circuit anda differential circuit. Each of the load resistors R3 and R4 on the laststage is set at 200 ohms. The input circuit 15 a of the intermediate ICchip 15, which is connected to the output circuit 14 b of the input-sideIC chip 14 as the IC chip on the succeeding stage, is configured by asource-follower t. The matching resistors R5 and R6 of 200 ohms are setin the input section.

The output circuit 14 b of the input-side IC chip 14 on the precedingstage and the input circuit 15 a of the intermediate IC chip 15 on thesucceeding stage are connected to each other through the internaltransmission paths 13 each formed on a mounting substrate/board 18 andhaving a characteristic impedance of 200 ohms. Thus, impedance matchingis achieved. The load resistors R3 and R4 on the preceding stage, whichare 200 ohms, and the matching resistors R1 and R6 of thesucceeding-stage input circuit 15 a, which are 200 ohms, allow theoutput load of the output circuit 14 b on the preceding stage to assume100 ohms.

Also in the case where the semiconductor integrated circuit isconfigured by field-effect transistors, reductions in the output currentof the output transistors and in the size thereof can be realized.

The field-effect transistors T1 to T7 may be MOS type transistors formedon a Si substrate or MES type transistors formed on a GaAs substrate.

Although the input matching resistors R5 and R6 are connected betweenthe source of the transistor T6 and the power source line and betweenthe source of the transistor T7 and the power source line, respectively,in the present embodiment, the input matching resistor may be connectedbetween the source and ground depending on the circuit scheme.

FOURTH EMBODIMENT

FIG. 7 shows the circuit configuration of a semiconductor deviceaccording to a fourth embodiment of the present invention. The fourthembodiment shows the case where the present invention is applied to amobile phone or a wireless LAN terminal. A mobile phone, such as a PDCpersonal digital cellular) or PHS (personal handyphone system), or awireless LAN terminal, such as a Bluetooth, is generally configured by asemiconductor device 300 including a transmitting circuit and areceiving circuit, such as shown in FIG. 7. The semiconductor device 300is configured by an RF block 300A and an IF/Baseband block 300B. The RFblock 300A includes an antenna switch 308, a low-noise amplifier 310, apower amplifier 319, mixers 311, 318 and the like and operates forprocessing of a high-frequency signal. The IF/Baseband block 300Bincludes a variable-gain amplifier 312, a quadrature demodulator 313, anA/D converter 314, a D/A converter 315, a quadrature modulator 316, adriver amplifier 317 and the like. In the PDC portable phone, the RFblock operates for processing of a signal of 800 MHz and the signal ischanged to 100 to 200 MHz through the mixer 311. In the Bluetooth the RFblock operates for processing of a signal of 2.4 GHz and the signal ischanged to 3 MHz through the mixer 311. In the receiving circuit of theRF block 300A, an RF receiving signal received through the antenna 301is passed through the antenna switch 308, band-pass filter 309, andlow-noise amplifier 310, applied to the mixer 311, mixed with a localoscillating signal from a local oscillator, and converted into an IFreceiving signal. In the transmitting circuit of the RF block 300A, anIF transmission signal is mixed with a local oscillating signal from thelocal oscillator 321 by the mixer 318 and converted into an RFtransmission signal. After being passed through the power amplifier 319,band-pass filter 320, antenna switch 308, and antenna 301, the RFtransmission signal is delivered. The input/output of the IC in the RFblock 300A described above has conventionally been effected through atransmission path formed on a printed-circuit board and having animpedance of 50 ohms. In the case of the present invention, on thereceiving circuit side, the impedances of a transmission path 302between the antenna switch 308 and the band-pass filter 309,transmission path 303 between the band-pass filter 309 and the low-noiseamplifier 310, and transmission path 304 between the low-noise amplifier310 and the mixer 311 are set at an impedance higher than 50 ohms (e.g.,100 ohms). On the transmitting circuit side, the impedance of atransmission path 305 between the mixer 318 and power amplifier 319 isset at an impedance higher than 50 ohms (e.g., 100 ohms), and theimpedances of a transmission path 306 between the power amplifier 319and the band-pass filter 320, and transmission path 307 between theband-pass filter 320 and antenna switch 308 are set at 50 ohms.Therefore, on the receiving circuit side, the receiving-side output ofthe antenna switch 308, the input/output of the band-pass filter 309,the input/output of the low-noise amplifier 310, and the input of themixer 311 are matched to an impedance higher than 50 ohms (e.g., 100ohms). Similarly, on the transmitting circuit side, the output of themixer 318 and input of the power amplifier 319 are matched to animpedance higher than 50 ohms (e.g., 100 ohms). On the transmittingcircuit side, the output of the power amplifier 319, the input/output ofthe band-pass filter 320, and the transmitting-side input of the antennaswitch 308 are matched to an impedance of 50 ohms.

As described above, it is possible to reduce the current dissipation bysetting the input/output of the ICs at an impedance higher than 50 ohmsto allow the impedances between the ICs to be matched.

Although the output of the antenna switch, the input/output of thelow-noise amplifier, the input of the mixer, and the like are matched toan impedance higher than 50 ohms in the above embodiment, the inputs oroutputs of other ICs, for example, the input/output of the band-passfilter 320 may be matched to an impedance higher than 50 ohms.

FIFTH EMBODIMENT

FIG. 8 shows the configuration of a semiconductor device according to afifth embodiment of the present invention. In a semiconductor device 400according to the fifth embodiment, an MCM 400A and an MCM 400B aremounted on a common mounting substrate/board. The two MCMs are connectedto each other through an inter-MCM transmission path 402C formed on thesame mounting substrate/board. On the MCM 400A to which a signal isinput through an external transmission path 401, an input-side IC 404A,an intermediate IC 405 and an output-side IC 406A are mounted, whereasinput/output transmission paths 402A, 402B and an internal transmissionpath 403 are formed thereon. On the MCM 400B, an input-side IC 404B, anintermediate IC 405 and an output-side IC 406B are mounted, whereasinput/output transmission paths 402A, 402B and an internal transmissionpath 403 are formed thereon. The MCM 400B outputs a signal through anexternal transmission path 401. Although the characteristic impedance ofthe input/output transmission path 402A is set at the same value of 50ohms as the characteristic impedance of the external transmission path,the characteristic impedances of the input/output transmission path402B, the internal transmission path 403, and the transmission path 402Cbetween MCMs are set at 200 ohms. Therefore, an input circuit 404Aa ofthe input-side IC 404A and output circuit 406Bb of the output-side IC406B are impedance matched to 50 ohms; whereas an output circuit 404Abof the input-side IC 404A, the input circuit 405 a and output circuit405 b of the intermediate IC 405, the input circuit 406Aa and outputcircuit 406Ab of the output-side IC 406A, the input circuit 404Ba andoutput circuit 404Bb of the input-side IC 404B, and the input circuit40613 a of the output-side IC 406B are impedance matched to 200 ohms.

Here, attention is paid to the MCM 400A and MCM 400B and it is foundthat the characteristic impedances of the input/output transmissionpaths 402A and 402B are set at different values from each other in thesesemiconductor devices. However, the present invention includes thesemiconductor device 400 as well as semiconductor devices represented bythe MCM 400A and MCM 400B. In other words, a semiconductor device inwhich the characteristic impedances of the input-side transmission pathand the output-side transmission path we set at different values fromeach other is also included in the scope of the present invention.According to the present invention, in the case where the characteristicimpedances of the input-side transmission path and the output-sidetransmission path are set at different values from each other, thecharacteristic impedance of at least one internal transmission path isset higher than that of the input/output transmission path having alower characteristic impedance.

The signal transmission paths that connect together internal ICs mayhave different characteristic impedances each corresponding to one of aplurality of groups of the signal transmission paths. In this case, theinput or output impedance of each of the ICs is so selected as to matchthe characteristic impedance of the corresponding signal transmissionpath.

Although the preferred embodiments of the present invention have thusbeen described heretofore, it is to be understood that the presentinvention is not limited to the above-described embodiments, and variousmodifications may be made without departing from the spirit and scope ofthe invention. For example, the case where the present invention isapplied to a flip-flop circuit used as the output section of the IC onthe preceding stage has been described in the above embodiments.Alternatively, however, the present invention is applicable to othercircuits such as an amplifier circuit.

1-15. (canceled)
 16. A semiconductor device comprising a plurality of ICelements including at least an input stage IC element and anoutput-stage IC element and mounted on a common mountingsubstrate/board, and signal transmission paths that connect each two ofsaid plurality of IC elements to achieve impedance matchingtherebetween, wherein that: an input impedance of said input-stage ICelement and an output impedance of said output-stage IC element areequal to a first impedance; and each of at least two of said pluralityof IC elements are impedance-matched to a corresponding one of saidsignal transmission paths at a matching impedance which is higher thansaid first impedance.
 17. The semiconductor device according to claim16, wherein said plurality of IC elements include a plurality of ICelement groups, each of which is mounted on a common mountingsubstrate/board.
 18. The semiconductor device according to claim 16,wherein said matching impedance differs between two of said signaltransmission paths.
 19. The semiconductor device according to claim 16,wherein at least one of said plurality of IC elements has a resistanceelement for said impedance matching in said input circuit and/or saidoutput circuit.
 20. The semiconductor device according to claim 19,wherein said output circuit is a differential circuit.
 21. Thesemiconductor device according to claim 19, wherein said input circuitis an emitter-follower circuit, and said resistance element is connectedbetween a base and a ground, or between a base and a power source. 22.The semiconductor device according to claim 19, wherein said inputcircuit is a source-follower circuit, and said resistance element isconnected between a gate and a ground, or between a gate and a powersource.
 23. The semiconductor device according to claim 16, wherein atleast one of said IC elements includes an ECL circuit.
 24. Thesemiconductor device according to claim 16, wherein at least one of saidIC elements is a bare chip.
 25. The semiconductor device according toclaim 16, wherein at least one of an input circuit of said input-stageIC element and an output circuit of said output-stage IC element isconnected to an external circuit through a coaxial cable.
 26. Thesemiconductor device according to claim 16, wherein a signal to be inputto said input-stage IC element has a transmission rate not less than 1Gbps or a frequency not less than 800 MHz.
 27. The semiconductor deviceaccording to claim 16, wherein said matching impedance is not more thanten times said first impedance.
 28. The semiconductor device accordingto claim 16, wherein said matching impedance is not less than doublesaid first impedance.
 29. A semiconductor device comprising a pluralityof IC elements including at least an input-stage IC element and anoutput-stage IC element and mounted on a common mountingsubstrate/board, and signal transmission paths that connect eachadjacent two of said plurality of IC elements to achieve impedancematching therebetween, wherein: an input impedance of said input-stageIC element and an output impedance of said output-stage IC element arefirst impedance and second impedance, respectively; and each of at leasttwo of said plurality of IC elements is impedance matched to acorresponding one of said signal transmission paths at a matchingimpedance higher than a lower one of said first and second impedances,wherein said matching impedance differs between two of said signaltransmission paths.
 30. The semiconductor device according to claim 29,wherein said plurality of IC elements include a plurality of IC elementgroups, each of which is mounted on a common mounting substrate/board.31. (canceled)
 32. The semiconductor device according to claim 29,wherein at least one of said plurality of IC elements has a resistanceelement for said impedance matching in said input circuit and/or saidoutput circuit.
 33. The semiconductor device according to claim 32,wherein said output circuit is a differential circuit.
 34. Thesemiconductor device according to claim 32, wherein said input circuitis an emitter-follower circuit, and said resistance element is connectedbetween a base and a ground, or between a base and a power source. 35.The semiconductor device according to claim 32, wherein said inputcircuit is a source-follower circuit, and said resistance element isconnected between a gate and a ground, or between a gate and a powersource.
 36. The semiconductor device according to claim 29, wherein atleast one of said IC elements includes an ECL circuit.
 37. Thesemiconductor device according to claim 29, wherein at least one of saidIC elements is a bare chip.
 38. The semiconductor device according toclaim 29, wherein at least one of an input circuit of said input-stageIC element and an output circuit of said output-stage IC element isconnected to an external circuit through a coaxial cable.
 39. Thesemiconductor device according to claim 29, wherein a signal to be inputto said input-stage IC element has a transmission rate not less than 1Gbps or a frequency not less than 800 MHz.
 40. The semiconductor deviceaccording to claim 29, wherein said matching impedance is not more thanten times said first impedance.
 41. The semiconductor device accordingto claim 29, wherein said matching impedance is not less than doublesaid first impedance.